The present invention relates to a method and an apparatus for evaluating a configuration of a wafer represented by a silicon wafer. The present invention also relates to a semiconductor device fabricating method, especially to a wafer enabling improvement in a yield in a device fabricating process using an exposure system, and a sorting method for the same.
Conventionally, a method for manufacturing a silicon wafer used as a semiconductor substrate material generally comprises a crystal growth process for producing a single crystal ingot by a Czochralski (CZ) method, a floating zone melting (FZ) method or the like, and a wafer manufacturing process for manufacturing a wafer by slicing this single crystal ingot and processing at least one main surface thereof into a mirror-like surface. To describe the process more detailedly, the wafer manufacturing process comprises, a slicing step of slicing the single crystal ingot to obtain a thin and disk-shaped wafer; a chamfering step of chamfering a peripheral edge portion of the wafer obtained through the slicing step to prevent cracking and chipping of the wafer; a lapping step of flattening this wafer; an etching step of removing machining deformation remaining in the so chamfered and lapped wafer; a polishing step of making a mirror surface of the wafer; and a cleaning step of cleaning the polished wafer to remove a polishing agent or dust particles deposited thereon. The main steps of the wafer manufacturing process are only listed above, and sometimes other steps such as a heat treatment step may be added, or the step sequence may be changed.
Recently, an integration level in a semiconductor device has been becoming increasingly higher because of the remarkable progress in the semiconductor device technology, and with this progress, a demand for quality of a silicon wafer or the like has also been becoming more severe. A semiconductor device is fabricated by using a mirror-polished wafer which has been subjected to the single crystal producing process and the wafer manufacturing process. In the device fabricating process, a step of forming a resist pattern is repeatedly performed 20 to 30 times. Recently, a higher integration level and higher performance in a semiconductor integrated circuit has been advanced remarkably, and in company with this tendency, more miniaturization of circuit patterns is required. Taking a DRAM (dynamic random access memory) as an example, in a 64M bit DRAM that is now in quantity production, a resist pattern of 0.25 xcexcm to 0.20 xcexcm is drawn. In a photolithography step, a KrF excimer laser (wavelength=248 nm) of ultraviolet radiation is used as a light source most frequently. Further, with miniaturization of patterns, also improvement in dimension accuracy and overlay accuracy is required. With this progress, also a demand for quality of a silicon wafer or the like used as a base for a device has been becoming more severe.
That is, this is because a higher integration level of a semiconductor device has brought out miniaturization of a device size, and for instance, slight undulation or the like on a silicon wafer may lead to errors in a device pattern during the photolithography step or other steps. In addition, in order to effectively use a wafer, there is required a wafer which has excellent flatness up to the utmost outer peripheral portion (the very limit of the chamfered portion) of its main surface.
As one of the important characteristics required to the silicon wafer as described above, there is a problem of shape quality thereof. The wafer shape quality includes various parameters such as a diameter, a thickness, parallelism, flatness, irregularities with a relatively longer cycle named sori, bow, warp or the like, irregularities with a cycle of several mm named undulation and surface roughness; recently, it is frequently evaluated by quality named global flatness or site flatness based on a back side reference or a front side reference as an index of flatness.
Especially, as the index of flatness, the global flatness based on the back side reference is named GBIR (Global Back Ideal Range); this is usually defined, assuming that a reference plane is prepared within a wafer surface, as a width between the maximum positional displacement and the minimum positional displacement against the reference plane, and corresponds to TTV (Total Thickness Variation) which is a conventional specification.
Also, the site flatness based on the back side reference is named SBIR (Site Back Ideal Range), and corresponds to LTV which was quite frequently used in the past. When a back surface of a wafer is used as a reference plane and further at each site a plane including a center of the site is employed as a focal plane, the SBIR is a sum of absolute values of the respective maximum displacements in the plus side and minus side from the focal plane in the site, which is evaluated for each site. Usually, in case of an 8-inch wafer or the like, this value is evaluated in an area having a site of the order of 20 mmxc3x9720 mm. The size of this site varies depending upon a diameter or specifications of a wafer.
Moreover, the site flatness based on the front side reference is named SFQR (Site Front Least Squares Range); this is a sum of absolute values of the respective maximum displacements in the plus side and minus side from the reference plane which is a flat plane in a site obtained by calculating data with the method of least squares, which is evaluated for each site within a prescribed site.
Further, quality named nanotopography has been taken seriously. The nanotopography (also named nanotopology) means irregularities with a wavelength of the order of from 0.1 mm to 20 mm and an amplitude of the order of from several nm to 100 nm; the evaluation method therefor is performed by evaluating a difference of altitude of irregularities (a PV value; peak to valley) on a wafer surface in a range of a square block having a side of the order of from 0.1 mm to 10 mm, or of a circular block having a diameter of the order of from 0.1 mm to 10 mm (this range is named WINDOW SIZE or the like). This PV value is also named Nanotopological Height or the like. As the nanotopography, it is desired that the maximum value of the irregularities present within the evaluated wafer surface is small. Usually, this value of a wafer is evaluated by the maximum value among PV values obtained through evaluation of a plurality of blocks with a square having a side of 10 mm, and when this value is 60 nm or less, it is determined that the evaluated wafer is a good chip.
Up to a design rule of 0.18 xcexcm in the device fabricating process, it was enough to manufacture a wafer that meets standard requirements under evaluation with the above-mentioned index, but as recently the design rule has been becoming increasingly severe with a specification of 0.15 xcexcm or even 0.13 xcexcm, when a wafer that meets the above standard requirements was used for fabricating an actual device, there sometimes took place decrease of its yield. Accordingly, there are required a wafer manufacturing method and a wafer evaluating method in which a wafer is prescribed by factors other than the above-mentioned indexes and specifications of severe design rules are carried out without any problem.
Especially, with the above-mentioned GBIR, SBIR, SFQR, or the like, although flatness at the middle side portion of a wafer can be precisely evaluated, flatness at a peripheral portion thereof, especially a portion in the vicinity of a boundary between a chamfered portion and a main surface of a wafer is sometimes not evaluated precisely.
For instance, in the device fabricating process, many processing machines such as an exposure system and other machines are used, and compatibility between a wafer holding chuck used in each machine and a configuration of a wafer to be processed has been becoming an issue. Matching between undulation and a peripheral shape of the chuck and those of the wafer is important, but it is impossible to evaluate the matching by the conventional indexes such as GBIR, SBIR, and SFQR.
There are now required indexes which can precisely evaluate the compatibility and the like between each device fabricating process, more particularly a chuck used in each processing machine and a wafer to be processed. Especially, when a severe specification of the design rule is applied to a wafer, it is necessary to more precisely evaluate the peripheral portion of the wafer.
Especially, there is a stepper (a popular name of a reduction projection step and repeat exposure system) wherein a wafer is stepped and exposed repeatedly to a projected figure through a mask pattern (a reticle patter); it was not necessarily possible to sort out wafers which are usable in the stepper in terms of configurations thererof by indexes such as SFQR. The same is also true for a scanning exposure system.
With the foregoing difficulties of the prior art in view, it is an object of the present invention to provide a method and an apparatus for evaluating a wafer configuration which, by evaluating quality of a wafer configuration from a different viewpoint from the conventional SFQR or the like, are capable of more precisely evaluating the peripheral portion of the wafer to manufacture a wafer suitable for each device fabricating process and improve production efficiency in the device fabricating process and the subsequent processes.
Another object of the present invention is to provide a device fabricating method, a wafer, and a wafer sorting method which, by evaluating quality of a wafer configuration from a different viewpoint from the conventional SFQR or the like using the above-mentioned evaluating method and apparatus, are capable of more precisely evaluating undulation on a wafer surface and the peripheral portion of a wafer to supply a wafer suitable for each device fabricating process, especially a process using an exposure system, and improve production efficiency in the device fabricating process and subsequent processes.
In order to achieve the above object, a first aspect of a method for evaluating a wafer configuration according to the present invention comprises the steps of: measuring a configuration of a wafer at positions with a prescribed space within a surface of the wafer; providing a first region within the wafer surface for calculating a reference line or a reference plane from the measured wafer configuration; calculating a reference line or a reference plane in the first region; providing a second region to be evaluated outside the first region; extrapolating the reference line or reference plane to the second region; analyzing a difference between the configuration of the second region and the reference line or reference plane within the second region; and calculating the analyzed difference as surface characteristics.
In the above inventive method, the second region is provided in a range of from a boundary of the first region to an edge portion of the wafer, differences (actually measured valuesxe2x80x94reference values) between configurations at a plurality of arbitrary positions within the second region (actually measured values) and the reference lines or reference planes at the positions (reference values) are analyzed, and the maximum value among the values of the analyzed differences (the positive maximum displacement amount or the positive maximum thickness difference) is calculated as the surface characteristic A (rise). (Note that this surface characteristic A (rise) may be called parameter A.)
In the above inventive method, the second region is provided in a range of from a boundary of the first region to an edge portion of the wafer, differences (actually measured valuesxe2x80x94reference values) between configurations at a plurality of arbitrary positions within the second region (actually measured values) and the reference line or reference plane at the positions (reference values) are analyzed, and the minimum value (the negative maximum value) among the values of the analyzed differences is calculated as the surface characteristic B (sag). (Note that this surface characteristic B (sag) may be called parameter B.).
A second aspect of the method for evaluating wafer configuration according to the present invention comprises the steps of: measuring a configuration of a wafer at positions with a prescribed space within a surface of the wafer; providing a first region on the wafer surface for calculating a reference line or a reference plane from the measured wafer configuration; calculating a reference line or a reference plane in the first region; obtaining differences between the reference line or the reference plane and actually measured values within the first region; and calculating a standard deviation a of the obtained differences as the surface characteristic C (undulation). (Note that the surface characteristic C (undulation) may be called parameter C).
Here, the wafer configuration measured at a plurality of positions with a prescribed space within the wafer surface is displacement (height or roughness) in the direction vertical to the wafer surface or a wafer thickness. Evaluation on the displacement in the direction vertical to the wafer surface makes it possible to perform evaluation based on the front side reference. Further evaluation on the wafer thickness makes it possible to perform evaluation based on the back side reference.
It is preferable to make the reference line of from the vicinity of the central portion of the wafer to a boundary of the first region within the first region by reading a configuration profile (that is, obtaining a configuration profile) of from the central portion of the wafer to the edge portion thereof.
The surface characteristics are preferably analyzed with a value obtained by averaging configuration profiles of from the central portion of the wafer to the edge portion thereof which are read at a plurality of positions on the wafer surface.
It is also possible to analyze the surface characteristics from respective configuration profiles which are read at a plurality of positions of from the central portion of the wafer to the edge portion thereof, and obtain an average value from a plurality of the analyzed surface characteristics.
Further, the reference plane of the first region is preferably made from data that are read within the extensive wafer surface of from the central portion of the wafer to the edge portion thereof.
In the conventional SFQR or the like, a wafer surface is divided into areas (sites) each about 20 mm square in which a reference plane is prepared for evaluation, but in this case, since a reference plane is prepared in a narrow area to be averaged, it is often impossible to accurately evaluate deterioration of an actual configuration or the like. Especially, in this conventional evaluating method, a configuration of the peripheral portion of the wafer cannot be evaluated accurately.
In the method according to the present invention, as shown in FIG. 1, a reference line or a reference plane is prepared in a global (extensive) region (a first region) for calculating a reference line or a reference plane from a basic configuration of a wafer; the reference line or reference plane is used by extrapolating it to a region to be evaluated such as the peripheral portion of the wafer (a second region) for analyzing the surface characteristics of the second region, or the reference line or reference plane is used in the first region to analyze the surface characteristics in the first region. Measuring a difference between the reference line or reference plane and the actual configuration, the measured maximum value is evaluated as a rise (A in FIG. 1), the measured minimum value as a sag (B in FIG. 1), and the dispersion of roughness in the first region (C in FIG. 1) as undulation. The undulation in the present invention is evaluated and quantified from a different point of view of the conventional undulation.
In other words, in the method according to the present invention, a reference line or a reference plane is prepared in an extensive specified region (a first region) on a wafer surface, which is an area larger than at least the site to be evaluated by the conventional SFQR or the like; the surface characteristics in the first region or in a region to be evaluated (a second region) other than the first region is evaluated based on the reference line or reference plane prepared in the extensive specified region (the first region).
As for the evaluation reference, a two-dimensional reference plane and a straight or curved reference line may be used, but it is necessary to use such a value as represents a whole (global) wafer configuration.
An apparatus for evaluating wafer a configuration according to the present invention comprises: a configuration measuring unit for measuring a configuration of a wafer at positions with a prescribed space on a surface of the wafer; a storage device for successively inputting and storing configuration data measured by the configuration measuring unit; and a surface characteristic calculating unit for reading the configuration data of from the central portion of the wafer to the edge portion thereof from the storage device, calculating a reference line or a reference plane in a region of from the central portion of the wafer to an arbitrary portion thereof, analyzing a difference between the reference line or the reference plane and an arbitrary position, and calculating the analyzed difference as surface characteristics.
The above-mentioned configuration measuring unit is preferably a displacement measuring unit for measuring displacement in the direction vertical to a surface of a test stand of a surface of the wafer placed on the test stand within a wafer surface, or a thickness measuring unit for measuring a thickness of a wafer held by a wafer holding jig within the wafer surface. The apparatus according to the present invention is advantageously used for carrying out the method according to the present invention.
In a device fabricating method according to the present invention, when fabricating a device on a wafer with an exposure system, the device is fabricated using the wafer having the surface characteristic A (rise) of 150 nm or less calculated by the above-mentioned evaluating method and apparatus.
Thus, the effect of rise in the peripheral portion of a wafer is great in the device fabricating process using an exposure system; it is preferable to make a value of the surface characteristic A (rise) obtained by the above-mentioned evaluating method as small as possible. Especially, it is effective to fabricate a device using an exposure system with a wafer of A=150 nm or less. It is preferable to make the rising components as small as possible, but it is not preferable to make sagging too large, so that the lower limit thereof is about xe2x88x9220 nm.
Further, when fabricating a device with an exposure system, it is preferable to fabricate the device using the wafer having the surface characteristic B (sag) of xe2x88x92300 nm or less, especially of xe2x88x92300 nm to xe2x88x92900 nm calculated by the above-mentioned evaluating method and apparatus.
It is most important for the wafer used in an exposure system to have no rise at the peripheral portion thereof, but too large sagging is not preferable, and the degree of slight sagging is preferable. Thus, there is very preferable for device fabrication a wafer of the order of xe2x88x92300 nm to about xe2x88x92900 nm, especially of the order of xe2x88x92500 nm to xe2x88x92600 nm with the above-mentioned indexes.
The wafer according to the present invention has the surface characteristic A (rise) of 150 nm or less and the surface characteristic B (sag) of xe2x88x92300 nm or less.
In brief, it is preferable that the surface characteristic A (rise) is 150 nm or less and the surface characteristic B (sag) is xe2x88x92300 nm or less in a wafer used in the device fabricating process with an exposure system.
Since the conventional wafer is not evaluated by the above-mentioned indexes, many sags are found in the peripheral portion thereof. For instance, in the conventional wafer the above parameter A is negative (xe2x88x92200 nm or less) and the parameter B is xe2x88x92700 nm or less. When the sags are eliminated from a wafer, the wafer is apt to have a rising configuration and the above parameter A becomes 200 nm or more.
However, since it is difficult to satisfy the above-mentioned wafer quality by the usual polishing, in the present invention the wafer peripheral portion is polished especially carefully to manufacture the wafer having the parameter ranges as described above.
There could be conceivably various methods for meeting the above requirements: for instance, a first method in which a work is polished in a state that a coating film made of material having a polishing rate slower than that of a work is formed on the work peripheral portion to adjust a polishing rate thereon; a second method in which a work is polished in a manner that an improved means for holding a work is employed, that is the size of a work holding plate is improved, or a work is chucked at its peripheral portion by a work holding plate with a hard central portion of a work holding region and a soft peripheral portion thereof, and a third method in which a front surface of a work is polished in a manner that a back coating is formed on a back surface of a work and the work is held at the back coating, and in this method peripheral sags can also be controlled by differentiating the thickness of the back coating between the peripheral portion of the wafer and the central portion thereof to change the polishing pressure on the peripheral portion thereof.
Further there are a fourth method in which a diameter of a wafer before the primary polishing is made larger than that of the finished product and sags in the peripheral portion are controlled by chamfering the wafer with decreasing the diameter thereof after the primary polishing; a fifth method in which a wafer is polished in such a way that by improving the polishing head the pressing force against the peripheral portion of a work is controlled independently from the central portion thereof; and a sixth method completely different from the above methods in which a peripheral configuration of a work is controlled by plasma etching the peripheral portion thereof after polishing.
However, even if a wafer is polished carefully under the manufacturing methods described above, it is frequently necessarily impossible to manufacture the wafer satisfying the above parameters A and B with certainty.
Accordingly, manufactured wafers are sorted before fabricating devices with them. That is, the wafer sorting method according to the present invention is for sorting a wafer on which devices are fabricated with an exposure system, wherein there is sorted the wafer having the surface characteristic A (rise) of 150 nm or less evaluated by the above-mentioned evaluating method.
Likewise, a wafer is evaluated and sorted in terms of the parameter B. That is, the inventive wafer sorting method is for sorting a wafer on which devices are fabricated with an exposure system, wherein further there is sorted the wafer having the surface characteristic B (sag) of xe2x88x92300 nm or less evaluated by the above-mentioned evaluating method.
Thus, by sorting wafers polished in the wafer manufacturing process, there can be obtained wafers more suitable for the device fabricating process, and the fabrication yield can further be improved.
In addition, fine irregularities on a wafer surface named nanotopography are becoming a problem, too. The same information as the above quality can be evaluated by using the surface characteristic C (undulation) of the inventive evaluating method too; the surface characteristic C (undulation) of 20 nm or less may lead to a wafer with an excellent surface state. The values for the surface characteristics are evaluated using data obtained by setting a boundary (an arbitrary position X) between the first region and the second region to a position of 30 mm away from the peripheral edge of the wafer; measurement of a wafer configuration is based on the data obtained by excluding the area with 1 mm in width along the peripheral portion of the wafer (excluding the chamfered portion).